In general, synchronous circuits are used in such a semiconductor device including a digital system as typified by an LSI. The system forming the semiconductor device is configured to operate in synchronization with a clock signal (a synchronization control signal). In the case of a large-scale system, for example, the system may be divided into multiple blocks. For example, the system may be divided into multiple medium-scale blocks, and the medium-scale blocks may be subdivided into small-scale blocks. In this case, a clock signal fed from a clock signal generator circuit branches from the medium-scale blocks to be distributed to the small-scale blocks through clock signal distribution lines.
Further, in recent high-speed, high-performance semiconductor devices, the operating frequency of a clock signal tends to be higher in order to increase operating speed. However, an increase in the operating frequency causes a problem in that a phase shift in the clock signal (skew) becomes a nonnegligible value with respect to the period of the clock signal so as to increase the risk of circuit malfunction.
Further, in recent semiconductor devices (LSIs), interconnects tend to be finer so as to increase the effect of interconnect delay. Further, there is also a growing problem of variations in interconnect delay due to variations in interconnect shape in manufacturing caused by microfabrication.
In view of the above, recent microfabricated, high-speed semiconductor devices containing synchronous digital systems have problems resulting from both an increase in the clock signal frequency (an increase in operating speed) and microfabrication (high integration). Therefore, control of clock skew has been highlighted as a problem important and difficult to solve.
Further, an interconnect delay in a clock signal distribution line is difficult to evaluate with accuracy at the stage of combining and placing the logic circuit cells of a semiconductor device (logic design stage) in designing the semiconductor device. Accordingly, controlling the effect of interconnect delay has also posed a great problem in designing the semiconductor device.
For example, as a method of controlling the above-described skew, it has been proposed to control timing by providing a semiconductor device with a predetermined circuit for skew control. Examples of methods of controlling the above-described skew include controlling timing of synchronization by providing a delay circuit, controlling timing with capacitance connected to a clock buffer, and extending the interconnect between inverters and performing control with the capacitance and resistance of the interconnect.
However, the above-described method that provides a semiconductor device with a circuit for skew control increases the complexity and size of the semiconductor device, thus posing a problem in size reduction and high integration of the semiconductor device. In particular, in the case of using fine interconnects, even if the above-described circuit for skew control is provided, there may be caused the problem of skew due to the interconnect delay of an interconnect connecting the circuit and another logic circuit cell. Thus, it is difficult to solve the problem of skew in highly integrated, high-speed semiconductor devices.
Therefore, in order to solve the above-described skew problems, there have been proposed methods of controlling skew using the fact that the resistance of an interconnect is changed by changing the cross-sectional area of the interconnect. (See, for example, Japanese Laid-Open Patent Application Nos. Hei 4-326411 and Hei 8-272480.) These methods control interconnect delay by, for example, changing the resistance of an interconnect by changing the width of the interconnect.
However, according to the above-described methods of Japanese Laid-Open Patent Application Nos. Hei 4-326411 and Hei 8-272480, since the interconnect delay is controlled with the cross-sectional area of an interconnect, there is the concern that the problem of reduction in the reliability of the interconnect due to electromigration may be caused in a fine (microfabricated) part of the interconnect. In particular, in microfabricated, highly integrated, high-performance semiconductor devices, the above-described problem of electromigration is more serious, so that there is the risk that the reliability of the semiconductor device may be reduced. Further, in a fine interconnect, there is a limit to the adjustable range of the cross-sectional area (interconnect delay) of the interconnect. Therefore, it is not practical to apply the above-described methods to highly integrated, high-performance semiconductor devices that operate at high speed.